An active matrix substrate is widely used in an active matrix type display device such as a liquid crystal display device, an EL (Electro Luminescence) display device, and the like. In an active matrix substrate used in a conventional active matrix type liquid crystal display device, a switching element such as a TFT (Thin Film Transistor) is provided on each of junctions between a plurality of scanning signal lines and a plurality of data signal lines which are disposed so as to cross each other. Further, a switching function of the TFT or the like allows an image signal to be suitably transmitted to each pixel (electrode) section connected to the TFT or the like. Further, there exists also an active matrix substrate arranged so that a storage capacitor element is provided on each of the pixel sections in order to prevent deterioration of an image signal which deterioration is caused by self-discharge of a liquid crystal layer or an OFF current of the TFT or the like during an OFF period of the TFT or the like and in order to use the active matrix substrate whose path receives various kinds of modulation signals in driving liquid crystal.
As an arrangement of an active matrix substrate used in a conventional active matrix type liquid crystal display device, the following substrate is known for example (see Patent Document 1 for example).
The following describes an active matrix substrate provided on a conventional active matrix type liquid crystal display device. FIG. 22 is a plan view illustrating a pixel of a conventional active matrix substrate.
In each pixel region 200 of the conventional active matrix substrate, a plurality of pixel electrodes 51 are provided in a matrix manner, and scanning signal lines 52 each of which supplies a scanning signal and data signal lines 53 each of which supplies a data signal are provided around each of the pixel electrodes 51 so that the scanning signal lines 52 and the data signal lines 53 cross each other. FIG. 22 illustrates one of the plurality of pixel electrodes 51.
Further, at a junction between each scanning signal line 52 and each data signal line 53, a TFT54 serving as a switching element connected to the pixel electrode 51 is provided. The scanning signal line 52 is connected to the gate electrode 55 of the TFT54. In response to a scanning signal, driving of the TFT54 is controlled. Further, the data signal line 53 is connected to a source electrode 66a of the TFT54 so that a data signal is inputted to the electrode 66a. Further, a drain wiring line 56 is connected to a drain electrode 66b of the TFT54. One electrode (storage-capacitor upper electrode) 57 of the storage capacitor element is connected to the drain wiring 56. Also, the storage-capacitor upper electrode 57 is connected to the pixel electrode 51 via a contact hole 58. Further, a storage capacitor (common) wiring 59 functions as the other electrode (storage-capacitor lower electrode) of the storage capacitor element.
An arrangement of the TFT54 of the active matrix substrate 200 is described as follows. First, the gate electrode 55 connected to the scanning signal line 52 is provided on a transparent insulating substrate and a gate insulating film is provided so as to cover the gate electrode. Further, a semiconductor layer is provided on the gate insulating film so that the semiconductor layer is overlapped on the gate electrode. The source electrode 66a and the drain electrode 66b are provided so as to partially cover the semiconductor layer.
However, the gate insulating layer arranged so as to have a single-layer structure in this manner raises the following problem. If a defect such as a pinhole, a crack, and the like of the gate insulating film occurs at the junction between the scanning signal line and the data signal line, each signal line is short-circuited. Thus, an arrangement in which the gate insulating film has a two-layer structure is proposed (see Patent Document 2).
However, the gate insulating film arranged so as to have a two-layer structure raises the following problem. Existence of a thick gate insulating film between the gate electrode and the semiconductor layer causes deterioration of a property of the TFT.
As a technique for avoiding the problem, Patent Document 3 discloses an arrangement in which: the gate insulating layer has a single-layer structure (silicon nitride film) in its portion corresponding to a lower portion of the semiconductor layer and has a plural-layer structure (silicon oxide film and silicon nitride film) in its other portion. In this technique, it is necessary to carry out etching or the like so as to remove the silicon oxide film corresponding to the lower portion of the semiconductor layer by a photolithography step and a dry-etching step.
[Patent Document 1]
    Japanese Unexamined Patent Publication Tokukaihei 9-152625 (Publication date: Jun. 10, 1997)[Patent Document 2]    Japanese Unexamined Patent Publication Tokukaihei 7-114044 (Publication date: May 2, 1995)[Patent Document 3]    Japanese Unexamined Patent Publication Tokukaihei 6-112485 (Publication date: Apr. 22, 1994)